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STL8NH3LL
N-channel 30V - 0.012 - 8A - PowerFLATTM Ultra low gate charge STripFETTM Power MOSFET
General features
Type STL8NH3LL

VDSS 30V
RDS(on) <0.015
ID 8A (1)
Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Very low gate charge Low threshold device In compliance with the 2002/95/EC Europen directive
PowerFLATTM(3.3x3.3) (Chip Scale Package)
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique "STripFETTM" technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Internal schematic diagram
Applications
Switching application
TOP VIEW
Order codes
Sales Type STL8NH3LL Marking 8NH3L Package PowerFLATTM (3.3 x 3.3) Packaging Tape & reel
March 2006
Rev 7
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Contents:
STL8NH3LL
Contents:
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STL8NH3LL
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID(1) ID (1) IDM
(2)
Absolute maximum ratings
Parameter Drain-Source Voltage (V GS = 0) Gate-Source Voltage Drain Current (continuous) at T C = 25C Drain Current (continuous) at T C=100C Drain Current (pulsed) Total Dissipation at T C = 25C Total Dissipation at T C = 25C Derating Factor Value 30 18 8 5 32 50 2 0.4 -55 to 150 Unit V V A A A W W W/C C
PTOT(3) PTOT(1)
TJ Tstg
Operating Junction Temperature Storage Temperature
1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. 3. The vaule is rated according Rthj-c
Table 2.
Symbol Rthj-case Rthj-pcb Rthj-pcb
(1) (2)
Thermal resistance
Parameter Thermal resistance junction-case (Drain) Thermal resistance junction-pcb Thermal resistance junction-pcb Value 2.5 42.8 63.5 Unit C/W C/W C/W
1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10sec 2. Steady state
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Electrical characteristics
STL8NH3LL
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS
On/off states
Parameter Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Test Condictions ID = 250A, VGS= 0 VDS = Max Rating, VDS = MaxRating @125C Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
IGSS VGS(th) RDS(on)
Gate Body Leakage Current VGS = 18V (VDS = 0) Gate Threshold Voltage Static Drain-Source On Resistance VDS= V GS, ID = 250A VGS= 10V, ID= 4A VGS= 4.5V, ID= 4A 1 0.012 0.0135
2.5 0.015 0.017
Table 4.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Condictions VDS =15V, ID = 4A Min. Typ. 30 965 285 38 9 3.7 3 12 Max. Unit S pF pF pF nC nC nC
VDS =25V, f=1 MHz, VGS=0
VDD=15V, ID = 8A VGS =4.5V (see Figure 7) f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain
Gate Input Resistance
0.5
1.5
2.5
1. Pulsed: pulse duration=300s, duty cycle 1.5%
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STL8NH3LL
Electrical characteristics
Table 5.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Test Condictions VDD =15V, ID= 4A, RG=4.7, VGS=4.5V (see Figure 13) Min. Typ. 15 32 18 8.5 Max. Unit ns ns ns ns
Table 6.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain Current Source-drain Current (pulsed) Forward on Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD=8A, V GS=0 ISD=8A, di/dt = 100A/s, VDD=20V, Tj=150C (see Figure 15) 24 17.4 1.45 Test Condictions Min Typ. Max 8 32 1.3 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Electrical characteristics
STL8NH3LL
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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STL8NH3LL Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized BVDSS vs temperature
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Test circuit
STL8NH3LL
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
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STL8NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL8NH3LL
PowerFLATTM (3.3 x 3.3) MECHANICAL DATA
mm. MIN. 0.80 TYP 0.90 0.02 0.20 0.23 0.30 0.328 0.12 3.30 2.50 1.25 2.65 3.30 1.40 1.325 0.975 0.850 0.250 1.50 0.049 2.75 0.098 0.38 0.009 MAX. 1.00 0.05 MIN. 0.031 inch TYP. 0.035 0.0007 0.0007 0.011 0.012 0.004 0.13 0.104 0.13 0.055 0.052 0.038 0.033 0.009 0.059 0.108 0.015 MAX. 0.039 0.0019
DIM. A A1 A3 b C C1 D D2 E E2 F F1 G G1
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STL8NH3LL
Revision history
5
Revision history
Table 7.
Date 21-Jul-2004 05-Oct-2004 19-Oct-2004 22-Nov-2004 21-Feb-2005 18-Apr-2005 14-Mar-2006
Revision history
Revision 1 2 3 4 5 6 7 First Release Values Changed New value inserted Document updated Final version Modified Figure 3, Figure 5., Figure 8.,Figure 9. New template Changes
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STL8NH3LL
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